Microprocessors, which include digital signal processors ("DSPs"), include execution units that perform the various operations directed by the instructions that make up the programs running on the microprocessors. The adder is one such execution unit, that performs addition operations. For example, a typical contemporary microprocessor adder performs two thirty-two bit additions. Thus, thirty-two bit wide operands, i.e., full word operands, are provided as inputs, and a full word sum result is provided as an output. The inputs are provided from registers in a register file, and the result is also provided to a register in the register file.
FIG. 1 depicts a typical full word addition, or ADD, operation, where the operands x and y, stored in registers r1 and r2, respectively, are added, and the result, z, is stored in register r3. This is expressed by, EQU ADD r1, r2, r3
While full word ADDs are essential in such microprocessors, another important microprocessor computation, especially in DSP applications, is the performance of multiple sub-word ADDs. Unfortunately, such ADD operations, for example of two sixteen bit, or half word, operands, are typically performed using full word adders that use carry-lookahead (CLA) schemes to compute the addition. One problem with this is that it breaks the carry path, and thus slows down the overall ADD operation.
Therefore, it would be desirable to provide an adder for inclusion in a microprocessor, which efficiently performs multiple sub-word ADD operations, without a great deal of additional circuitry, as compared with prior art adders. The present invention provides such an adder.